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innovative power tm - 1 - www.active-semi.com copyright ? 2012 active-semi, inc. rev 4, 14-nov-12 high performance activepsr tm primary switching regulator features ? patented primary side regulation technology ? no opto-coupler ? suitable operation frequency up to 85khz ? best-in-class constant voltage, constant current accuracy ? low emi ? proprietary fast startup circuit ? built-in soft-start circuit ? integrated line and primary inductance compensation ? integrated programmable output cord resistance compensation ? line under-voltage, output over-voltage, output short-circuit and over-temperature protection ? complies with all global energy efficiency and cec average efficiency standards ? adjustable power from 2w to 6.3w ? minimum external components ? tiny sot23-6 package applications ? chargers for cell phones, pdas, mp3, portable media players, dscs, and other portable devices and appliances ? rcc adapter replacements ? linear adapter replacements ? standby and auxiliary supplies general description the act364 belongs to the high performance patented activepsr tm family of universal-input ac/dc off-line controllers for battery charger and adapter applications. it is designed for flyback topology working in discontinuous conduction mode (dcm). the act364 meets all of the global energy efficiency regulations (cec, european blue angel, and us energy star standards) while using very few external components. the act364 ensures safe operation with complete protection against all fault conditions. built-in protection circuitry is provided for output short- circuit, output over-volt age, line under-voltage, and over temperature conditions. the act364 activepsr tm is optimized for high performance, cost-sensitive applications, and utilizes active-semi?s pr oprietary primary-side feedback architecture to provide accurate constant voltage, constant current (cv/cc) regulation without the need of an opto-coupler or reference device. integrated line and primary inductance compensation circuitry provides accurate constant current operation despite wide variations in line voltage and primary inductance. integrated output cord resistance compensation further enhances output accuracy. the act364 achieves excellent regulation and transient response, yet requires less than 150mw of standby power. the act364 is optimized for compact size 2w to 6.3w charger applications. it is available in space- saving 6 pin sot23-6 package. figure 1: simplified application circuit act364
act364 rev 4, 14-nov-12 innovative power tm - 2 - www.active-semi.com copyright ? 2012 active-semi, inc. pin configuration pin descriptions part number temperature range package pins packing method top mark act364us-t -40c to 85c sot23-6 6 tape & reel fscs sot23-6 act364us-t ordering information pin name description 1 sw switch drive. switch node for the external npn tr ansistor. connect this pin to the external power npn?s emitter. this pin also supplies current to vdd during startup. 2 gnd ground. 3 bd base drive. base driver fo r the external npn transistor. 4 vdd power supply. this pin provides bias power fo r the ic during startup and steady state op eration. 5 fb feedback pin. connect this pin to a resist or divider network from the auxiliary winding. 6 cs current sense pin. connect an external resistor (r cs ) between this pin and ground to set peak current limit for the primary sw itch. the peak current limit is set by (0.396v 0.9) / r cs . for more detailed information, see application information.
act364 rev 4, 14-nov-12 innovative power tm - 3 - www.active-semi.com copyright ? 2012 active-semi, inc. absolute maximum ratings c electrical characteristics (v dd = 14v, v out = 5v, l p = 1.5mh, n p = 140, n s = 7, n a = 19, t a = 25c, unless otherwise specified.) c : do not exceed these limits to prevent damage to the device. ex posure to absolute maximum rati ng conditions for long periods m ay affect device reliability. parameter value unit vdd, bd, sw to gnd -0.3 to + 28 v maximum continuous vdd current 100 ma fb, cs to gnd -0.3 to + 6 v continuous sw current internally limited a maximum power dissipation (derate 4.5mw/ ? c above t a = 50 ? c) 0.45 w junction to ambient thermal resistance ( ja ) 220 ? c/w operating junction temperature -40 to 150 ? c storage junction -55 to 150 ? c lead temperature (soldering, 10 sec) 300 ? c parameter symbol test conditions min typ max unit supply vdd turn-on voltage v ddon v dd rising from 0v 17.6 18.6 19.6 v vdd turn-off voltage v ddoff v dd falling after turn-on 5.25 5.5 5.75 v supply current i dd v dd = 14v, after turn-on 1 2 ma start up supply current i ddst v dd = 14v, before turn-on 25 45 a bd current during startup i bdst 1 a internal soft startup time 10 ms oscillator switching frequency f sw 100% v outcv @ full load 80 khz 25% v outcv @ full load 40 maximum switching frequency f clamp 85 100 110 khz maximum duty cycle d max 65 75 85 % feedback effective fb voltage v fb 2.176 2.200 2.224 v fb leakage current i fblk 100 na output cable resistance compensation dv comp no r cord between vdd and sw 0 % r cord = 300k 3 r cord = 150k 6 r cord = 75k 9 r cord = 33k 12
act364 rev 4, 14-nov-12 innovative power tm - 4 - www.active-semi.com copyright ? 2012 active-semi, inc. parameter symbol test conditions min typ max unit current limit sw current limit range i lim 100 600 ma cs current limit threshold v cslim t off_delay = 0 380 396 412 mv leading edge blanking time 200 300 ns driver outputs switch on-resistance r on i sw = 50ma 1.6 3 ? sw off leakage current v sw = v dd = 22v 5 a protection vdd latch-off voltage v ddovp v ddon +2 v ddon +3 v ddon +4 v thermal shutdown temperature 135 ? c thermal hysteresis 20 ? c line uvlo i fbuvlo 116 a electrical characteristics cont?d (v dd = 14v, v out = 5v, l p = 1.5mh, n p = 140, n s = 7, n a = 19, t a = 25c, unless otherwise specified.) functional block diagram
act364 rev 4, 14-nov-12 innovative power tm - 5 - www.active-semi.com copyright ? 2012 active-semi, inc. as shown in the functional block diagram, to regulate the output voltage in cv (constant voltage) mode, the act364 compares the feedback voltage at fb pin to the internal reference and generates an error signal to the pre-amplifier. the error signal, after filtering out the switching transients and compensated with the internal compensation network, modulates the external npn transistor peak current at cs pin with current mode pfwm (pulse frequency and width modulation) control. to regulate the output current in cc (constant current) mode, the oscillato r frequency is modulated by the output voltage. sw is a driver output that drives the emitter of an external high voltage npn transistor. this base- emitter-drive method makes the drive circuit the most efficient. fast startup vdd is the power supply terminal for the act364. during startup, the act364 typically draws only 20 a supply current. the startup resistor from the rectified high voltage dc rail supplies current to the base of the npn transistor. this results in an amplified emitter current to vdd through the sw pin via active-semi's proprietary fast-startup circuitry until it exceeds the v ddon threshold 19v. at this point, the act364 enters internal startup mode with the peak current limit ramping up in 10ms. after switching starts, the output voltage begins to rise. the vdd bypass capacitor must supply the act364 internal circuitry and the npn base drive until the output voltage is high enough to sustain vdd through the auxiliary winding. the v ddoff threshold is 5.5v; therefore, the voltage on the vdd capacitor must remain above 5.5v while the output is charging up. constant voltage (cv) mode operation in constant voltage operation, the act364 captures the auxiliary flyback signal at fb pin through a resistor divider network r5 and r6 in figure 6. the signal at fb pin is pre-amplified against the internal reference voltage, and the secondary side output voltage is extracted based on active-semi's proprietary filter architecture. this error signal is then am plified by the internal error amplifier. when the secondary output voltage is above regulation, the error amplifier output voltage decreases to reduc e the switch current. when the secondary output voltage is below regulation, the error amplifier output voltage increases to ramp up the switch current to bring the secondary output back to regulation. the output regulation voltage is determined by the following relationship: where r fb1 (r5) and r fb2 (r6) are top and bottom feedback resistor, n s and n a are numbers of transformer secondary an d auxiliary turns, and v d is the rectifier diode forward drop voltage at approximately 0.1a bias. standby (no load) mode in no load standby mode, the act364 oscillator frequency is further reduced to a minimum frequency while the current pulse is reduced to a minimum level to minimize standby power. the actual minimum switching frequency is programmable with an output preload resistor. loop compensation the act364 integrates loop compensation circuitry for simplified application design, optimized transient response, and minimal external components. output cable resistance compensation the act364 provides programmable output cable resistance compensation during constant voltage regulation, monotonically adding an output voltage correction up to predetermined percentage at full power. there are four levels to program the output cable compensation by connecting a resistor (r10 in figure 3) from the sw pin to vdd pin. the percentage at full power is programmable to be 3%, 6%, 9% or 12%, and by using a resistor value of 300k, 150k, 75k or 33k respectively. if there is no resistor connection, there is no cord compensation. this feature allows for better output voltage accuracy by compensating for the output voltage droop due to the output cable resistance. constant current (cc) mode operation when the secondary output current reaches a level set by the internal current limiting circuit, the act364 enters current limit condition and causes the secondary output volta ge to drop. as the output voltage decreases, so does the flyback voltage in a proportional manner. an internal current shaping circuitry adjusts the switching frequency based on the flyback voltage so that the transferred power remains proportional to the output voltage, resulting functional description (1) d a s 2 fb 1 fb outcv v n n r r 1 v 20 . 2 v ? ? ? ? ? ? ? ? ? + =
act364 rev 4, 14-nov-12 innovative power tm - 6 - www.active-semi.com copyright ? 2012 active-semi, inc. in a constant secondary side output current profile. the energy transferred to the output during each switching cycle is ?(l p i lim 2 ) , where l p is the transformer primary inductance, i lim is the primary peak current, and is the conversion efficiency. from this formula, the constant output current can be derived: where f sw is the switching frequency and v outcv is the nominal secondary output voltage. the constant current operation typically extends down to lower than 40% of nominal output voltage regulation. primary inductance compensation the act364 integrates a built-in proprietary (patent-pending) primary inductance compensation circuit to maintain constant current regulation despite variations in transformer manufacturing. the compensated range is 7%. primary inductor current limit compensation the act364 integrates a primary inductor peak current limit compensation circuit to achieve constant input power over line and load ranges. protection the act364 incorporates multiple protection functions including over-vol tage, over-current and over-temperature. output short circuit protection when the secondary side output is short circuited, the act364 enters hiccup mode operation. in this condition, the vdd voltage drops below the v ddoff threshold and the auxiliary supply voltage collapses. this turns off the act364 and causes it to restart. this hiccup behavior continues until the short circuit is removed. output over voltage protection the act364 includes output over-voltage protection circuitry, which shuts down the ic when the output voltage is 40% above the normal regulation voltage for 4 consecutive switching cycles. the act364 enters hiccup mode when an output over voltage fault is detected. over temperature shutdown the thermal shutdown circuitry detects the act364 die temperature. the typical over temperature threshold is 135c with 20c hysteresis. when the die temperature rises above this threshold the act364 is disabled until the die temperature falls by 20c, at which point the act364 is re-enabled. typical application design example the design example below gives the procedure for a dcm flyback converter using the act364. refer to application circuit in figure 6, the design for a charger application starts with the following specification: the operation for the circuit shown in figure 3 is as follows: the rectifier bridge d1 ? d4 and the capacitor c1/c2 convert the ac line voltage to dc. this voltage supplies the primary winding of the transformer t1 and the startup resistor r7/r8. the primary power current path is formed by the transformer?s primary winding, the npn transistor, the act364 internal mosfet and the current sense resistor r9. the network consisting of capacitor c4 and diode d6 provides a vdd supply voltage for act364 from the auxiliary winding of the transformer. c4 is the decoupling capacitor of the supply voltage and energy storage component for startup. the diode d8 and the capacitor c5 rectifies and filters the output voltage. the resistor divider consisting of r5 and r6 programs the output voltage. the minimum and maximum dc input voltages can be calculated: functional description cont?d ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = outcv sw 2 cs p outcc v f r 9 . 0 v 396 . 0 l 2 1 i (2) v 90 f 8 . 6 2 % 70 ) ms 5 . 3 50 2 1 ( 5 2 85 2 c ) t f 2 1 ( p 2 v 2 v 2 in c l out 2 acmin indcmin ? ? = ? ? = (3) v 375 265 2 v 2 v acmax indcmax = = = (4) input voltage range 85vac - 265vac, 50/60hz output power, p o 5w output voltage, v outcv 5.0v ocp current, i outmax 1.3a full load current, i outfl 1a transformer efficiency, xfm 0.89 system efficiency cc, system 0.69 system efficiency cv, 0.70
act364 rev 4, 14-nov-12 innovative power tm - 7 - www.active-semi.com copyright ? 2012 active-semi, inc. v 75 5 8 . 0 40 ) 4 . 0 5 ( 375 v v ) v v ( v v outcv drev ds outcv indcmax ro = ? + = ? + = (5) 140 t / nh 76 mh 5 . 1 a l n 2 le p p = = = 7 . 2 3 . 0 40 . 0 5 1 38 . 0 14 v v v v v v n n cord ds outcv r da dd s a = + + + + = + + + + = 16 n n f 9 . 0 n n ) v v ( i l v i l s p sw s p ds outcv pk p indcmin pk p > ? < + + mh 5 . 1 khz 75 ma 7 . 352 % 45 90 f i d v l sw pk indcmin p = = ma 7 . 352 % 45 36 . 79 2 d i 2 i in pk = = = ma 36 . 79 % 70 90 1 5 v i v i indcmin outpl outcv in = = = (6) (7) (8) (9) k 87 . 8 9 . 49 20 . 2 7 . 2 ) 4 . 0 5 ( 20 . 2 r v n n ) v v ( v r 1 fb fb s a ds outcv fb 2 fb = ? + = ? + = (16) f 120 mv 50 khz 75 45 . 0 1 v f d i c ripple sw outcc out = = = (17) (10) 7 140 20 1 n n n n p p s s = = = (11) 19 7 7 . 2 n n n n s s a a = = = (13) k 9 . 49 245122 1 5 . 1 140 19 k r l n n r cs p p a 1 fb = = (15) () () r 983 . 0 89 . 0 69 . 0 75 5 . 1 5 3 . 1 1 396 . 0 9 . 0 f l v i i v 9 . 0 r xfm system sw p out outmax outfl cslim cs = ? ? ? ? ? ? + = ? ? ? ? ? ? ? ? + = (14) where is the estimated circuit efficiency, f l is the line frequency, t c is the estimated rectifier conduction time, c in is empirically selected to be 2 6.8f electrolytic capacitors based on the 3f/w rule of thumb. when the transistor is tu rned off, the voltage on the transistor?s collector consists of the input voltage and the reflected voltage from the transformer?s secondary winding. there is a ringing on the rising top edge of the flyback voltage due to the leakage inductance of the transformer. this ringing is clamped by a rcd network if it is used. design this clamped voltage as 50v below the breakdown of the npn transistor. the flyback voltage has to be considered with selection of the maximum reverse voltage rating of secondary rectifier diode. if a 40v schottky diode is used, then the flyback voltage can be calculated: where v ds is the schottky diode forward voltage, v drev is the maximum reverse voltage rating of the diode and v outcv is the output voltage. the maximum duty cycle is set to be 45% at low line voltage 85v ac and the circuit efficiency is estimated to be 70%. then the full load input current is: the maximum input primary peak current at full load base on duty of 45%: the primary inductance of the transformer: act364 needs to work in dcm in all conditions, thus n p /n s should meet the auxiliary to secondary turns ratio n a /n s : where v da is diode forward voltage of the auxiliary side and v r is the resister voltage. an efd15 transformer gapped core with an effective inductance a le of 76nh/t 2 is selected. the number of turns of the primary winding is: the number of turns of secondary and auxiliary windings can be derived when np/ns=20: the current sense resistance (r cs ) determines the current limit value based on the following equation: the voltage feedback resistors are selected according to below equation: where k is ic constant and k = 245122. when selecting the output capacitor, a low esr electrolytic capacitor is recommended to minimize ripple from the current ripple. the approximate equation for the output capacitance value is given by: a 470f electrolytic capacitor is used to keep the ripple small. pcb layout guideline good pcb layout is critical to have optimal performance. decoupling capacitor (c4), current sense resistor (r9) and feedback resistor (r5/r6) should be placed close to v dd , cs and fb pins respectively. there are two main power path loops. one is formed by c1/c2, primary winding, npn transistor and the act364. the other is the secondary winding, rectifier d8 and output capacitors (c5). keep these loop areas as small as possible. connect high curr ent ground returns, the input capacitor ground lead, and the act364 g pin typical application cont?d (12)
act364 rev 4, 14-nov-12 innovative power tm - 8 - www.active-semi.com copyright ? 2012 active-semi, inc. 1.5s typical application cont?d to a single point (star ground configuration). v fb sampling waveforms act364 senses the output voltage information through the v fb waveforms. proper v fb waveforms are required for ic to operate in a stable status. to avoid mis-sampling, 1.5s blanking time is added to blank the ringing period due to the leakage inductance and the circuit parasitic capacitance. figure 2 is the recommended v fb waveform to guarantee the correct sampling point so that the output information can be sent back into the ic to do the appropriate control. figure 2:
act364 rev 4, 14-nov-12 innovative power tm - 9 - www.active-semi.com copyright ? 2012 active-semi, inc. figure 3: universal vac input, 5v/1a output charger item reference description qty manufacturer 1 u1 ic, act364us-t, sot23-6 1 active-semi 2 c1, c2 capacitor, electrolytic, 4.7f/400v, 8 12mm 2 ksc 3 c3 capacitor, ceramic,1000pf/500v,1206,smd 1 poe 4 c4 capacitor, electrolytic, 4.7f/35v, 5 11mm 1 ksc 5 c5 capacitor, electrolytic, 680f/10v, 8 12mm 1 ksc 6 c9 capacitor, ceramic,1000pf/50v,0805,smd 1 poe 7 bd1 bridge,b6s,600v/0.5a,mdi,smd 1 panjit 8 d5,d6 diode, ultra fast, fr107,1000v/1.0a, do-41 2 good-ark 9 d8 diode, schottky, 40v/3a, sb340, do-15 1 good-ark 10 l1 axial inductor, 1.5m h, 0410, dip 1 amode tech 11 q1 transistor, npn, 700v,1.5a, d13003, to-126 1 huawei 12 fr1 fusible resistor, 1w, 10 ? , 5% 1 ty-ohm 13 r1,r4 chip resistor, 22 ? , 0805, 5% 2 ty-ohm 14 r2 chip resistor, 750k, 1206, 5% 1 ty-ohm 15 r3 chip resistor, 470 ? , 1206, 5% 1 ty-ohm 16 r5 chip resistor, 49.9k, 0805, 1% 1 ty-ohm 17 r6 chip resistor, 8.87k, 0805, 1% 1 ty-ohm 18 r7,r8 chip resistor, 5.1m ? , 1206, 5% 2 ty-ohm 19 r9 chip resistor, 1.0 ? , 1206, 1% 1 ty-ohm 20 r10 chip resistor, 162k, 0805, 5% 1 ty-ohm 21 r11 chip resistor, 1.1k, 0805, 5% 1 ty-ohm 22 r13 chip resistor, 10 ? , 0805, 5% 1 ty-ohm 23 t1 transformer, l p = 1.5mh7%, efd15 1 table 1: act364 bill of materials
act364 rev 4, 14-nov-12 innovative power tm - 10 - www.active-semi.com copyright ? 2012 active-semi, inc. typical performance ch aracteristics cont?d (circuit of figure 6, unless otherwise specified.) act364-012 internal mosfet r on vs. temperature r on ( ? ) 2.4 2.0 1.6 1.2 0.8 0.4 0.0 act364-007 act364-008 vdd on/off voltage vs. temperature start up supply current vs. temperature 20.5 16.5 14.5 12.5 10.5 8.5 6.5 4.5 18.5 v ddon and v ddoff (v) temperature (c) 0 25 50 75 act364-009 fb voltage vs. temperature v fb (v) 2.25 2.20 2.15 2.10 2.05 2.00 v ddon v ddoff temperature (c) 0 25 50 75 28 26 24 22 20 18 16 14 i ddst (a) temperature (c) 0 25 50 75 temperature (c) 0 25 50 75 act364-010 normalized i lim vs. temperature 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 normalized i lim (ma) temperature (c) 0 25 50 75
act364 rev 4, 14-nov-12 innovative power tm - 11 - www.active-semi.com copyright ? 2012 active-semi, inc. package outline sot23-6 package outline and dimensions d b e1 e e e1 a1 a2 a c l 0.2 symbol dimension in millimeters dimension in inches min max min max a - 1.450 - 0.057 a1 0.000 0.150 0.000 0.006 a2 0.900 1.300 0.035 0.051 b 0.300 0.500 0.012 0.020 c 0.080 0.220 0.003 0.009 d 2.900 bsc 0.114 bsc e 1.600 bsc 0.063 bsc e1 2.800 bsc 0.110 bsc e 0.950 bsc 0.037 bsc e1 1.900 bsc 0.075 bsc l 0.300 0.600 0.012 0.024 0 8 0 8 active-semi, inc. reserves the right to modify the circuitry or specifications without notice. user s should evaluate each product to make sure that it is suitable for their applicat ions. active-semi products are not intended or authorized for use as critical components in life-support dev ices or systems. active-semi, inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. active-semi and its logo are trademarks of active-semi, inc. for more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com . is a registered trademark of active-semi.

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